Current state of the art integrated circuit CMOS (complementary metal oxide semiconductor) technology supports the implementation of digital-based receiver systems for use in high data rate (e.g. 28 Gb/s and higher) wireline communications systems. These wireline communications systems include, for example, backplane transceivers used in data processing systems and networking infrastructure such as interact-protocol (IP) routers and switches. Some advantages of using a digital-based receiver design include, for example, the ability to realize digital functions in low power and low die area using state of the art CMOS processes such as 14 nm CMOS and beyond. Further, digital-based receiver designs can efficiently support line modulation schemes that are more complex than the standard 2-level “Non-Return to Zero” (NRZ) modulation scheme that is currently used in a wide majority of backplane wireline communication transceivers up to data rates of 28 Gb/s. Indeed, evolving industry standards are now migrating to 4-level line modulation to improve the spectral efficiency, or equivalently, to increase the maximum data rate than can be transmitted through a bandlimited wireline channel. By way of example, the current 56 Gb/s industry data rate for medium-reach electrical backplane applications is supported by 4-level PAM (pulse amplitude modulation). A digital receiver design is ideal to realize a 56 Gb/s 4-level PAM data transceiver system because such design can readily implement complex digital functions, such as line equalization and digital clock recovery functions, which are necessary to accurately process and decode 4-level modulated signals.